VLSI and hardware engineering interview questions

  1. Explain why & how a MOSFET works
  2. Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes (a) with increasing Vgs (b) with increasing transistor width (c) considering Channel Length Modulation
  3. Explain the various MOSFET Capacitances & their significance
  4. Draw a CMOS Inverter. Explain its transfer characteristics
  5. Explain sizing of the inverter
  6. How do you size NMOS and PMOS transistors to increase the threshold voltage?
  7. What is Noise Margin? Explain the procedure to determine Noise Margin
  8. Give the expression for CMOS switching power dissipation
  9. What is Body Effect?
  10. Describe the various effects of scaling
  11. Give the expression for calculating Delay in CMOS circuit
  12. What happens to delay if you increase load capacitance?
  13. What happens to delay if we include a resistance at the output of a CMOS circuit?
  14. What are the limitations in increasing the power supply to reduce delay?
  15. How does Resistance of the metal lines vary with increasing thickness and increasing length?
  16. You have three adjacent parallel metal lines. Two out of phase signals pass through the outer two metal lines. Draw the waveforms in the center metal line due to interference. Now, draw the signals if the signals in outer metal lines are in phase with each other
  17. What happens if we increase the number of contacts or via from one metal layer to the next?
  18. Draw a transistor level two input NAND gate. Explain its sizing (a) considering Vth (b) for equal rise and fall times
  19. Let A & B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later than signal B. To optimize delay, of the two series NMOS inputs A & B, which one would you place near the output?
  20. Draw the stick diagram of a NOR gate. Optimize it
  21. For CMOS logic, give the various techniques you know to minimize power consumption
  22. What is Charge Sharing? Explain the Charge Sharing problem while sampling data from a Bus
  23. Why do we gradually increase the size of inverters in buffer design? Why not give the output of a circuit to one large inverter?
  24. In the design of a large inverter, why do we prefer to connect small transistors in parallel (thus increasing effective width) rather than lay out one transistor with large width?
  25. Given a layout, draw its transistor level circuit. (I was given a 3 input AND gate and a 2 input Multiplexer. You can expect any simple 2 or 3 input gates)
  26. Give the logic expression for an AOI gate. Draw its transistor level equivalent. Draw its stick diagram
  27. Why don’t we use just one NMOS or PMOS transistor as a transmission gate?
  28. For a NMOS transistor acting as a pass transistor, say the gate is connected to VDD, give the output for a square pulse input going from 0 to VDD
  29. Draw a 6-T SRAM Cell and explain the Read and Write operations
  30. Draw the Differential Sense Amplifier and explain its working. Any idea how to size this circuit? (Consider Channel Length Modulation)
  31. What happens if we use an Inverter instead of the Differential Sense Amplifier?
  32. Draw the SRAM Write Circuitry
  33. Approximately, what were the sizes of your transistors in the SRAM cell? How did you arrive at those sizes?
  34. How does the size of PMOS Pull Up transistors (for bit & bit- lines) affect SRAM’s performance?
  35. What’s the critical path in a SRAM?
  36. Draw the timing diagram for a SRAM Read. What happens if we delay the enabling of Clock signal?
  37. Give a big picture of the entire SRAM Layout showing your placements of SRAM Cells, Row Decoders, Column Decoders, Read Circuit, Write Circuit and Buffers
  38. In a SRAM layout, which metal layers would you prefer for Word Lines and Bit Lines? Why?
  39. How can you model a SRAM at RTL Level?
  40. What’s the difference between Testing & Verification?
  41. For an AND-OR implementation of a two input Mux, how do you test for Stuck-At-0 and Stuck-At-1 faults at the internal nodes? (You can expect a circuit with some redundant logic)
  42. What is Latch Up? Explain Latch Up with cross section of a CMOS Inverter. How do you avoid Latch Up?
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48 Comments on VLSI and hardware engineering interview questions

  1. Ruchi Gupta
    Posted 1/24/2004 at 8:45 pm | Permalink

    Do you also post the answers to these (Hardware)questions?

  2. Posted 1/24/2004 at 8:48 pm | Permalink

    Ruchi, I only post what I have, and this set of questions came without answers. If you and other readers know the answers, you can post the comments here, and I will add them to the original documents.

  3. Karthik Ramachandran
    Posted 1/27/2004 at 1:36 am | Permalink

    All answers can be found in ” Principles of CMOS VLSI design by Neil and Kamran

  4. mushtaque
    Posted 3/17/2004 at 12:37 am | Permalink

    i have forgotten my administrator password in Win 2000n server ,and file system is NTFS how can i break that and work normally plz say it fast

  5. Prafulla
    Posted 4/7/2004 at 8:22 am | Permalink

    Use Digital Integrated Circuits A Design Prespective BY Jan M. Rabaey for answer to all Questions……Njoyyyy

  6. Subodh Taigor
    Posted 4/11/2004 at 11:23 pm | Permalink

    Here are the books:
    1. Design of CMOS analog integrated Circuits: For Mosfet operation, secondry
    effects, short-channel effects, mos-capacitances, Layout issues.
    2. Digital Integrated Circuits A Design Prespective BY Jan M. Rabaey:
    For:Read chapters:Invertor, CMOS combinational logic, Interconnects,
    CMOS sequential logic, Memory(last chapter)
    **for moise margins fundas read “kang”

  7. Bala
    Posted 4/18/2004 at 12:05 pm | Permalink

    For Question 6, I think the PMOS transistors should be sized more than NMOS transistors

  8. Tina
    Posted 4/20/2004 at 11:30 am | Permalink

    Hi,
    has anyone appeared in the Wipro’s exam held in Jan 2004 and Nov 2003 for the M.Tech/MS/ME for VLSI candidates. Can someone help in in this regards.

    Thanks.

  9. Junaid
    Posted 4/21/2004 at 1:45 pm | Permalink

    Here is the stick diagram for NAND,NOR and NOT gates.Got it by searching on google.

    VCC VCC
    | | | |
    | | | |
    P -x——–x———x————————
    | | |
    | |____/|\________ C
    | | |
    N -x—————–x————————-
    | | |
    | | |
    VSS B A

    2 INPUT NAND

    VCC
    | | |
    | | |
    P –x—————-x—–
    | | |
    | ____/|\_|____ C
    | | |
    N –x——-x——–x—–
    | | | |
    | | | |

    VSS A B VSS

    2 INPUT NOR

    VCC
    | |
    | |
    P –x—–x–
    | |
    | |__ B
    | |
    N –x—–x–
    | |
    | |

    VSS A

    INVERTER

  10. Junaid
    Posted 4/21/2004 at 1:46 pm | Permalink

    Sorry i showed up right in comment box …but not after posting.

  11. Posted 4/21/2004 at 1:51 pm | Permalink

    Follow this link for stick diagram

  12. Posted 4/21/2004 at 3:52 pm | Permalink
  13. Rekha
    Posted 5/11/2004 at 9:23 pm | Permalink

    hi guys does anyone have the answers ready? i know its in the book
    but wud appreciate if anyone can provide some answers. thanks!

  14. Anynonymous
    Posted 12/15/2004 at 5:14 am | Permalink

    Q14: Dynamic Power dissipation increases.
    Q15: Resistance is directly propotional to length and inversly propotional to area.So higher metals has lesser resistance.Increasing L increases the resistance.
    Q17:Increase in contact resistance.
    Q27:NMOS passes clean zero and a bad one while PMOS passes clean 1 and bad zero(Hint:Vt loss)
    Q42:Paratic Tx act as tyristors.Chances of triggering this thyristor.
    Put sufficient well contacts.

  15. Kundan Srivastava
    Posted 12/16/2004 at 1:08 am | Permalink

    u can find all the needfull in :
    1)Principles of CMOS VLSI Design : Neil Weste
    2)Microelectronics circuits : Adel A. Sedra,K.smith
    3)Digital Integrated Circuit : Kang

  16. G.Madhusudhan
    Posted 5/10/2005 at 4:24 am | Permalink

    Hi, any guys can help me in getting interview questions on digital sequential logic, F/Fs, timing constraints, formal verification.

  17. Nitin
    Posted 5/10/2005 at 11:03 am | Permalink

    Thanx, this page has certainly provided a background to withstand interview for our project assignment on Vlsi. But additional details are required (other than kang & neil weste’s book)for that can anyone find from
    -Cmos Analog Circuit Design
    by Phillip E. Allen and Douglas R. Holberg
    -RF Cmos Integrated Circuits
    by Thomas H. Lee

    fist book is ideal for newcomers in analog domain (everything is properly arranged ADDitional topics ADC & DAC)& second for those who wants to work in RF mode.

  18. the lung
    Posted 6/5/2005 at 5:39 pm | Permalink

    how do you increase the noise margins?

    The only thing that i can think of is increase the width of the nmos (k_R ratio), but then that also increases your V_IH

  19. nagaprasad
    Posted 6/26/2005 at 10:35 pm | Permalink

    hi…analog designers
    these answers can be found in simpler way in the book
    “AnalogICdesign” by baker
    all the best to all of u

  20. Roshan
    Posted 7/7/2005 at 1:21 am | Permalink

    Can u explain me about latch up proble in cmos gates

  21. narasimha
    Posted 7/13/2005 at 8:46 am | Permalink

    answer for 19 th question:
    connect b signal to the transistor(mos) which is nearer to the supply,bec it will reduces the charge sharing problem between the source of one Txr and drain of another Txr.the reason for the charge sharing is that the capacitance formed between the two layers

    if any queries please free to mail me
    narasimha_828@yahoo.co.in

  22. Subodh Taigor
    Posted 7/26/2005 at 10:44 pm | Permalink

    Vt of MOS decreases with temperature, But current decreases. How come?

  23. ranjit
    Posted 12/20/2005 at 12:37 pm | Permalink

    Answer for Question 6:
    Threshold voltages are increased by making the voltage of the NMOS bulk silicon negative with respect to the source terminal of the array, and the PMOS bulk more positive vis–vis the drain of the array.

  24. Krishnamraju Kurra
    Posted 12/27/2005 at 12:22 pm | Permalink

    Comment 14 says that answer to question 17 is “Increase in contact resistance”.
    I think the resistance decreases. Look at the ‘contacts’ between the metal lines as ‘resistances in parallel’ with one another. If one conatact gives a resistance of R between the meatl lines, then four contacts would give a resistance of R/4.

  25. Krishnamraju Kurra
    Posted 12/27/2005 at 12:30 pm | Permalink

    I would recommend “CMOS: Circuit Design, Layout, and Simulation” by “Dr. Jake Baker”. Check http://www.cmosedu.com/ and the authors website for streaming video lectures on CMOS circuits.

  26. Krishnamraju Kurra
    Posted 12/27/2005 at 12:42 pm | Permalink

    Answer to question on comment # 22.
    Both resistance and threshold volatge are effected by temperature.
    As temperature goes up threshold goes down and resistance goes up.
    Effect of increase in resistance in more than the effect of decrease in threshold above a certain temprature, thats why we see a decrease in current.
    Think in terms of mobility of the majority carriers to understand why resistance goes up.

  27. Prashant
    Posted 1/26/2006 at 12:20 am | Permalink

    Ans to Q14

    Considering the Punchthru and DIBL (because of which gate looses the control over the transistor operation) the increase in Vdd has to be restricted. As well the HOT electron effect also takes place.

    You can refer the book ‘Digital Integrated Circuits, A Design Perspective’ by ‘Jan M. Rabaey’

    Prashant
    (IITM)

  28. Ygchen
    Posted 2/6/2006 at 6:52 pm | Permalink

    Answer to question on comment # 22.

    Around room temperature, the threshold of a MOSFET reduces with temperature, but the carrier mobility increase with temperature.
    These two effects influence the drain current simutaneously, but the mobility change dominates, so the overall effects shows the current decrease.

  29. Ygchen
    Posted 2/7/2006 at 1:18 am | Permalink

    Sorry for the typo error, the mobility decreases with temperature around room temperature.

  30. NIKHIL AHUJA
    Posted 4/8/2006 at 2:59 pm | Permalink

    anser to ques 21:
    we can reduce power dissipation of mos ckts by reducing the supply voltage and reducing the frequency .

  31. NIKHIL AHUJA
    Posted 5/7/2006 at 1:26 pm | Permalink

    hi..to all
    ans to 24…i think its a better to connect them in parallel instead of one large width transistor because it reduces the area…

  32. Prashant
    Posted 5/7/2006 at 2:01 pm | Permalink

    in reply to comment 31 i would like to say that.. instead of saying it reduces the area.. its better if we say it reduces the stray capacitances..
    the circuit performace is the first criteria for the designer.. not area

  33. Atul
    Posted 5/23/2006 at 5:04 am | Permalink

    Ans to Q21. The ways to minimize power consumption of CMOS is by 1) Optimizing Vt, 2) process Scaling and 3) Fabrication Advancements

  34. Suraj
    Posted 12/25/2006 at 7:46 pm | Permalink

    Corrected the typos:

    First - This set of questions and the feedback from everyone is wonderful.
    Additional Answer for question 24: Longer the width you encounter IR-drop since the poly/gate is high resistance. There is signal degradation along the long width. True, for capacitive reasons and from layout perspective (area) are the two reasons to avoid long widths. Too short widths are not good either since it can be susceptible to delta w-variations.

  35. mansi
    Posted 1/17/2007 at 2:11 pm | Permalink

    Ans#9:
    The Body Effect describes the effect of Source to Bulk volateg on the Threshold voltage of the mosfet.

    If there is even a little potential difference between the source and the bulk, this will increase the threshold volatge value.

    Vtn = Vto + γ(√Vsb + 2φ )- √2φ
    where Vto = zero bias volatge , Vsb =source to bulk volatge, γ = body effect parameter , φ = surface potential .

  36. uma
    Posted 3/8/2007 at 1:18 am | Permalink

    After drawing the CMOS layout where actually it’s given as input for next process.What is the difference bten. pre and post layout

  37. Ashwath & Raghavendra
    Posted 4/1/2007 at 3:57 pm | Permalink

    Refer Pg no. 173–176 in “CMOS digital Intergrated Circuits ” ……Kang

  38. chiranjeevi
    Posted 4/12/2007 at 9:10 am | Permalink

    MOSFET is type of transistor.first of all,let us discuss about the FET then MOSFET.FET means field effect transistor.hence it can be noyed that transistor is effected by the applied field

  39. Mohammad Usaid Abbasi
    Posted 6/17/2007 at 7:32 am | Permalink

    19. Let A & B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later than signal B. To optimize delay, of the two series NMOS inputs A & B, which one would you place near the output?

    Ans. The input which is coming late is tied close to output.Take a look at the pull-down circuitry :

    __out
    _|
    A -|_
    _|- C
    B -|_
    |
    Gnd

    -> Lets say that A is coming at 3ns and it takes 1ns to discharge a node, and B is coming at 4ns and it takes 1ns to discharge the node.A will not starts discharging the node out until and unless node C is discharged which happens only after 5 ns (4+1).So total time to discharge out is 6ns.But if A is coming at 4ns and B is coming at 3ns,then total time to discharge C is 4ns (3+1) and to discharge out is 5ns.

    ——usaidabbasi@gmail.com

  40. Mohammad Usaid Abbasi
    Posted 6/17/2007 at 7:33 am | Permalink

    19. Let A & B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later than signal B. To optimize delay, of the two series NMOS inputs A & B, which one would you place near the output?

    Ans. The input which is coming late is tied close to output.Take a look at the pull-down circuitry :

    __out
    _|
    A -|_
    _|- C
    B -|_
    |
    Gnd

    -> Lets say that A is coming at 3ns and it takes 1ns to discharge a node, and B is coming at 4ns and it takes 1ns to discharge the node.A will not starts discharging the node out until and unless node C is discharged which happens only after 5 ns (4+1).So total time to discharge out is 6ns.But if A is coming at 4ns and B is coming at 3ns,then total time to discharge C is 4ns (3+1) and to discharge out is 5ns.

    ——usaidabbasi@gmail.com

  41. Mohammad Usaid Abbasi
    Posted 6/17/2007 at 7:36 am | Permalink

    23.Why do we gradually increase the size of inverters in buffer design? Why not give the output of a circuit to one large inverter?

    Ans.. If we directly give the output of the circuit to one large inverter then the output of the circuit might not be able to drive the
    inverter completely resulting in large delays…

  42. Mohammad Usaid Abbasi
    Posted 6/17/2007 at 7:40 am | Permalink

    15. How does Resistance of the metal lines vary with increasing thickness and increasing length?

    R = pl/A (p is resistivity here)

    if you increase the length charge carriers have to go longer (motion get retarded due to brownian movement,increase in resistance).If you increase thickness carriers face less congestion so moves freely (decrease in resistance)

    usaidabbasi@gmail.com

  43. Raja
    Posted 7/29/2007 at 3:43 pm | Permalink

    Transmission gate works if and only if the both nmos and pmos triggers.. if any of the mos switches does not switch.. then the output goes into impedence state (which may be high or low)

  44. Raja
    Posted 7/29/2007 at 3:47 pm | Permalink

    Q34 The PMOS Pull up transistors act when we need to write in the SRAM. as one of the node turns high the other turns low (coz both the inverters are cross soupled with two pass transistors) in order for the node to turn high it needs the transistor pull up. so pmos transistor is used to pull up.

  45. Raja
    Posted 7/29/2007 at 3:55 pm | Permalink

    Q31. Differential Sense amplifier(SA) is used in order to differentiate the two inputs(BL & /BL) and amplify the signal of the bitlines, example.. If we see a small voltage rise (around 0.6v) in the bitlines which in turn the output of the 6T memory cell.. then the differential amplifier amplifies the signal to 1.2V (that is the voltage produced to S.A)so if we use the inverter instead of the Amplifier, as we know that inverter can be used for amplification of the signal.. but the problem here can be the output is inverted and the the comparison of both bit and bit bar is not possible..

  46. Raja
    Posted 7/29/2007 at 4:12 pm | Permalink

    Q12 Delay increases if we increase the Load Cap. by eqn.

    Td(delay) = An *(CL / Bn)

    here Td is directly proportional to CL so as CL increases Td increases
    where
    An = Process const. for a specific Vdd.
    Bn = Beta of NMOS.

  47. andy
    Posted 1/13/2008 at 2:50 pm | Permalink

    well for question 6 detailed answer:

    for an NMOS:
    as vt decreses Vds increases

    therefore Ids icreases or qualitatively the effective channel length of NMOS decreses.

    thus to increase vt for nmos increase channel length and vice versa for PMOS

    -Bolo Yo…….if u read neil and weste thoruoghly it willl put u in good stead…….

  48. Mohammad Usaid Abbasi
    Posted 4/25/2008 at 12:45 pm | Permalink

    12. What happens to delay if you increase load capacitance?

    Delay increases…
    I=Cdv/dt
    or dt=Cdv/I
    or dt proportonal to C

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