Hardware architecture interview questions

  1. Are you familiar with the term MESI?
  2. Are you familiar with the term snooping?
  3. Describe a finite state machine that will detect three consecutive coin tosses (of one coin) that results in heads.
  4. In what cases do you need to double clock a signal before presenting it to a synchronous state machine?
  5. You have a driver that drives a long signal & connects to an input device. At the input device there is either overshoot, undershoot or signal threshold violations, what can be done to correct this problem?
  6. For a single computer processor computer system, what is the purpose of a processor cache and describe its operation?
  7. Explain the operation considering a two processor computer system with a cache for each processor.
  8. What are the main issues associated with multiprocessor caches and how might you solve it?
  9. Explain the difference between write through and write back cache.
  10. What are the total number of lines written in C/C++? What is the most complicated/valuable program written in C/C++?
  11. What compiler was used?
  12. Have you studied busses? What types?
  13. Have you studied pipelining? List the 5 stages of a 5 stage pipeline. Assuming 1 clock per stage, what is the latency of an instruction in a 5 stage machine? What is the throughput of this machine ?
  14. How many bit combinations are there in a byte?
  15. What is the difference between = and == in C?
  16. Are you familiar with VHDL and/or Verilog?
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22 Comments on Hardware architecture interview questions

  1. Aniket
    Posted 6/9/2006 at 6:39 am | Permalink

    Suggestion fo Question No. 16.:

    VHDL stands for Very high speed integrated circuit Hardware Discription Language. VHDL is used to design vary large scale integrated circuits. It can simulate the wave form output of the proposed circuit.

    Verilog is another hardware discription language but more powerful than VHDL.
    Verilog can be used to design analog circuits as well. VHDL has limilation of designing digital circuits only.

  2. Aniket
    Posted 6/9/2006 at 6:47 am | Permalink

    Answer for Question 14. :

    There can be 2^8 combinations of bits in a byte.

  3. vijay
    Posted 6/17/2006 at 2:34 am | Permalink

    for question no 15:
    “=” it assigns the value( of right side variable) to the left side.

    where as”==” will compare the two operands.This will be used in Descion making statements.

  4. sunny
    Posted 8/23/2006 at 5:11 am | Permalink

    for question num. 12
    Basically there are 3 types of busses they r :
    1 system bus,
    2 data bus and
    3 control bus in any kind of microprocessor or computer

  5. sunny
    Posted 8/23/2006 at 5:14 am | Permalink

    for question 6

    basically cache memory is a temporary memory tat is used by microprocessor. Also i m doutful about this question

  6. Potty
    Posted 10/13/2006 at 3:45 am | Permalink

    Question 13:

    Stage1: Instruction Fetch
    Stage2: Decode Stage 1
    Stage3: Decode Stage 2
    Stage4: Execute
    Stage5: Write back

    Computer Organization & Architecture, Designing for performance, William Stallings

  7. hackcrackvirus
    Posted 10/18/2006 at 7:40 am | Permalink

    For que no.6

    Cache is required for temp storage due to vast difference in operating speed of processor and main memory.

  8. Obaid
    Posted 10/24/2006 at 9:29 pm | Permalink

    sunny said,
    Wrote on August 23, 2006 @ 5:11 am

    for question num. 12
    Basically there are 3 types of busses they r :
    1 system bus,
    2 data bus and
    3 control bus in any kind of microprocessor or computer

    System bus is just a data bus in a computer. You forgot about address bus.

  9. Obaid
    Posted 10/24/2006 at 9:30 pm | Permalink

    Question 13:

    Most moder texts list the following stages of a pipeline:

    Instruction fetch
    Instruction decode and register fetch
    Memory access
    Register write back

  10. Obaid
    Posted 10/24/2006 at 9:32 pm | Permalink

    Question 13:

    Latency = 5, throughput = 1

  11. Obaid
    Posted 10/24/2006 at 9:33 pm | Permalink

    MESI represents the 4 states of cache:


    This method is used in cache coherency and is applied in the Pentium family of processors.

  12. Posted 10/31/2006 at 11:13 pm | Permalink

    “What are the total number of lines written in C/C++? What is the most complicated/valuable program written in C/C++? ”

    I dont really know if there is single correct answer to this question but I feel a closer answer could be GCC. In 1985 The first version of GCC was able to compile itself. Even today I think most versions of GCC are able to compile itself. GCC as we all know is a highly respected C\C++ compiler and its contributions to open source and C\C++ is unparalleled.

    Another answer which I can think of is the Linux Kernel (as of now)

  13. Posted 10/31/2006 at 11:21 pm | Permalink

    “How many bit combinations are there in a byte?”

    Generally collection of 8 bits is called a byte. But the number can certainly vary depending on architecture of machines. I mean there are/were machines for which a byte != 8 bits.

  14. das
    Posted 12/7/2006 at 3:04 pm | Permalink

    Cache memory is a small high-speed memory. It is used for temporary storage of data & information between the main memory and the CPU (center processing unit). The cache memory is only in RAM

  15. palani
    Posted 3/1/2007 at 7:15 am | Permalink

    six roles of active dirretory forest and domain

    1 . domain naming operating master - forest

    2 . global catloge sever - forest

    3 . sehma master - forest

    4 . rid relative master - domain

    5 . pdc immodulat - domain

    6 . infrastructure master - domain

  16. Abhijit Singh
    Posted 3/13/2007 at 4:51 am | Permalink

    Problem (3)–>

    H1 H2 H3
    Start——->S1——>S2——>End/Final State
    | / /
    Tail | Tail / /

  17. Ramalingam
    Posted 9/27/2007 at 7:28 am | Permalink

    Cache memory is a small temporary memory in cpu.which has two types called level1 and level2. Level1 is used in cpu to have quick operation. But level2 is on the motherboard. if the processor check the catch memeory then get the data from where means that term is called catch hit else catch miss.

  18. Bingmo
    Posted 5/13/2008 at 1:04 am | Permalink

    Snooping is method used in multi-core parallel processing environment to keep the data access by different caches consistence.

  19. Anjaz
    Posted 10/14/2008 at 9:01 am | Permalink


    In Write thru Cache the write from cache to main memory(RAM) occurs at the same time when cache is modified. so here the data loss due to power failure and some critical conditions could be avoided

    In write back Cache the write from cache to Main memory occurs only after the cache is been updated or it requires to move the page from cache to main memory.here the advt is that time could be saved by saving two write occuring at the same time.

    And also remember the memory near to processor is easier to acces rather than the farther 1 and ie why caches are classifies as L1 cACHE AND L2 Cache

  20. Anjaz
    Posted 10/14/2008 at 9:03 am | Permalink


    ‘=’ is used to assign some values to a variable(a memory location) or pass values from 1 variable to other . Its basically used to assign.

    ‘==’ is used to compare between two variables or values . it is a condition checking ‘EQUAL TO’

  21. Anjaz
    Posted 10/14/2008 at 9:08 am | Permalink


    Processor Cache is used to increase the performance of the computer processor.

    more the distance of memory from processor slower the performance of the processor .

    their are many techniques implemented to make the procesor acces the memory faster and the succes one is use of cache ….
    their are many cache algorithms also implemented .

    Processor cannot work independently it requires program to run or execute and these programs are stored in memory so processor requires to be in touch with memory constantly so their will be consider loss of time(performance) if memory access tooks much time so this make the requiremnt of Cache to be present.

  22. Anjaz
    Posted 10/14/2008 at 9:11 am | Permalink


    Multiprocessor cache s/m isuues:

    Multi processor means able to handle multitasking . So their must be an Bus arbitration rule and also a good protocol to handle the issue.
    cache HiT and cache MISS must be considered into account carefully.

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